The duty cycle of a periodic signal refers to the ratio between the duration of a logic high state in a period of the periodic signal and the duration of the period of the periodic signal. A periodic signal is also referred to as a clock signal.
Duty cycle distortion (DCD) causes the duty cycle of a clock signal to vary from an ideal value. For example, DCD may cause the duty cycle of a clock signal to be greater than or less than an ideal value of 50%. DCD in a clock signal may be caused, for example, by variations between the pull-up currents and the pull-down currents through transistors in a circuit that generates the clock signal. DCD in the clock signal is dependent on variations in the process, the supply voltage, and the temperature of the circuit that generates the clock signal.
Many data transmission systems use clock signals to transmit and receive data signals. Duty cycle distortion (DCD) in a clock signal used by a data transmitter may cause the data transmitter to generate jitter in a data signal. Jitter in the data signal may cause a data receiver that receives the data signal to sample incorrect data bits in the data signal.